The present invention relates generally to nonvolatile memory devices and, more particularly, to a flash memory device capable of preventing flash memory cells from being over-erased and an erase method thereof.
Nonvolatile memory devices have become increasingly popular, especially flash memory devices. FIG. 1 shows a conventional flash memory cell. The flash memory cell has source and drain regions 2 and 3, respectively, formed in a P-type semiconductor substrate 1 (or bulk), a floating gate 6 formed over a channel region 5 and between the source and drain regions 2 and 3, respectively. A thin (100 xc3x85) insulator 4 is interposed between the floating gate 6 and the substrate 1. A control gate 8 is formed over the floating gate 6 with a second insulator 7 interposed therebetween. The control gate 8 is coupled to a word line.
Table 1 shows the conventional approach to programming, reading, erasing, and erase-verifying the flash memory cell shown in FIG. 1.
The flash memory cell is programmed by applying a ground (0V) to the source 2 and the bulk 1, a high voltage of +10V to the control gate 8, and a positive voltage of +5V to the drain 3 resulting in appropriate hot electron generation. The above-described voltages cause a sufficient amount of negative charges to accumulate in the floating gate 6 creating a (xe2x88x92) potential. The (xe2x88x92) potential forces a threshold voltage of the flash memory cell to be increased during reading.
During a read operation, a voltage of +5V is applied to the control gate 8 and the ground voltage is applied to the source 3. Under these conditions, the channel of the programmed memory cell is nonconductive. That is, no current flows from the drain 3 to the source 2 via the channel 5. At this time, the programmed memory is in an off state, and its threshold voltage, as illustrated in FIG. 2, is distributed within about +7V to +9V.
Flash memory cells in a sector are simultaneously erased by means of the so-called Fowler-Nordheim (F-N) tunneling mechanism. According to the F-N tunneling mechanism, a negative high voltage of about xe2x88x9210V is applied to the control gate 8 of each memory cell transistor and a positive voltage between about +6V to +9Vxe2x80x94suitable to make the F-N tunnelingxe2x80x94is applied to the substrate 1. Under this bias condition, the drain and source 2 and 3, respectively, of each cell are maintained at a floating state as shown in Table 1. This erase scheme is termed Negative Gate and Bulk Erase (NGBE). A strong electric field between 6 to 7 MV/cm is generated between the control gate 8 and the bulk 1 under the above-described bias condition, so that negative charges accumulated in the floating gate 6 are discharged into the source 2 through the thin insulator 5. The negative charges force a reduction in the threshold voltage of the memory cell during reading.
The particulars of various bulk erase methods associated with a flash memory device are disclosed in U.S. Pat. No. 5,781,477 entitled xe2x80x9cFLASH MEMORY SYSTEM HAVING FAST ERASE OPERATIONxe2x80x9d, U.S. Pat. No. 5,132,935 entitled xe2x80x9cERASURE OF EEPROM MEMORY ARRAYS TO PREVENT OVER-ERASED CELLSxe2x80x9d, U.S. Pat. No. 5,220,533 entitled xe2x80x9cMETHOD AND APPARATUS FOR PREVENTING ERVERERASURE IN A FLASH CELLxe2x80x9d, U.S. Pat. No. 5,513,193 entitled xe2x80x9cNON-VOLATITLE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CHECKING THE THRESHOLD VALUE OF MEMORY CELLSxe2x80x9d, and U.S. Pat. No. 5,805,501 entitled xe2x80x9cFLASH MEMORY DEVICE WITH MULTIPLE CHECKPOINT ERASE SUSPEND LOGICxe2x80x9d, incorporated herein by reference.
After performing the above-described NBGE operation, an erase verification operation is performed to check whether a threshold voltage of each flash memory cell in the sector exists in a target threshold voltage range corresponding to the on state (e.g., +1V to +3V). During the erase verification operation, as shown in Table 1, an erase verification voltage of about +3V is applied to the control gate 8, a voltage of about +5V to the drain 3, and the ground voltage (0V) to the source 2 and the bulk 1.
Typically, the threshold voltage of the erased memory cell is distributed in a range of +1V to +3V. However, when all of the memory cells in the sector are simultaneously erased, a threshold voltage of one or more flash memory cells can be lowered below +1V. When this happens the flash memory cell is termed an over-erased cell. The over-erased cell can be cured by an erase repair operation that shifts the threshold voltage of the over-erased cell back to a target threshold voltage range of the on cell (e.g., +1V to +3V).
The erase repair operation is carried out by applying the ground voltage (0V) to the source 2 and the bulk 1 of the over-erased cell, a voltage of about +3V to the control gate 8, and a voltage of about +5V the drain 3. This bias condition accumulates charges in the floating gate 6 of an amount less than those accumulated during a program operation. The erase repair operation, as illustrated in FIG. 2, results in the threshold voltage of the over-erased memory cell shifting back into the target threshold voltage distribution (e.g., +1V to +3V).
One problem associated with the above-described erase method is the length of time that it takes to perform the additional erase repair operation. This is because the repair operation increases the overall time it takes to erase the memory cell. As well known to those skilled in the art, such a problem arises when excess electric field is applied across the floating gate of the flash memory cell.
Applying a weaker electric field can lower the time it takes to perform an NGBE erase operation. The overall erase time, however, remains unchanged because while applying a weaker electric field results in none to fewer over-erased cells, eliminating the time required to perform the over-erase repair operation, the actual erase operation takes longer.
It is an object of the present invention to overcome the problems associated with conventional flash memory devices. It is another object of the present invention to provide a flash memory device capable of reducing the total erase operation time and an erase method therefor.
It is yet another object of the present invention to provide a flash memory device capable of minimizing the number of flash memory cells over-erased during an erase operation.
According to an aspect of the present invention, there is provided a method for erasing flash memory cells in an array formed on a semiconductor substrate, each cell having and ON and an OFF state and a source, drain, and control gate. The method comprises applying a first electric field between the control gate of a corresponding memory cell and the semiconductor substrate during a first interval and step-wise incrementing the first electric field during the first interval. The method further comprises applying a second electric field between the control gate of the corresponding memory cell and the semiconductor substrate during a second interval and maintaining constant the second electric field during the second interval.
Applying the first electric field includes applying the first electric field when a threshold voltage of the corresponding memory cell is higher than a verify voltage.
Applying a second electric field includes applying a second electric field when a threshold voltage of one of the memory cells is equal to or greater than a verify voltage. during the second interval in which a threshold voltage of at least one memory cell reaches the verify voltage.
The verify voltage is greater than a maximum value of a target threshold voltage range corresponding to the ON state.
Applying the second electric field includes applying the second electric field equal in strength to the first electric field when a threshold voltage of at least one memory cell is equal to or greater than the verify voltage.
Applying the first electric field further comprises erasing the memory cells by applying a negative voltage to corresponding control gates and a positive bulk voltage to the semiconductor substrate and verifying whether a threshold voltage of the corresponding memory cells is equal to or greater than the verify voltage. Applying the first electric field further comprises increasing the positive bulk voltage by a predetermined voltage when the threshold voltage of the corresponding memory cells is over the verify voltage and repeatedly erasing, verifying, and increasing until the threshold voltage of at least one memory cell is equal to or greater than the verify voltage.
According to another aspect of the present invention, there is provided a flash memory device that comprises an array of memory cells arranged in row and columns. A row selecting circuit selects at least one row responsive to a row address. A column selecting circuit selects at least one column responsive to a column address. A sense amplifier circuit senses and amplifies data bits in memory cells arranged in the selected at least one row and column. A high voltage generating circuit generates a bulk voltage applied to a bulk during an erase operation. An erase controller receives the data bits from the sense amplifier circuit. The erase controller checks if a threshold voltage of at least one of the cells reaches a verify voltage over a maximum value of a target threshold voltage range corresponding to an erased state. The erase controller controls the high voltage generating circuit so that the bulk voltage generated therefrom is stepwise increased by a predetermined voltage when the threshold voltage of the at least one cell is over the verify voltage. The erase controller controls the high voltage generating circuit such that the bulk voltage is maintained constant when the threshold voltage of the at least one cell reaches the verify voltage.
The constantly maintained bulk voltage is equal to a voltage applied to the bulk when the threshold voltage of the at least one cell reaches the verify voltage.
The flash memory device further comprises a row counter for generating the row address and a column counter for generating the column address. The erase controller increments the column counter when all of the columns are selected and increments the row counter when all of the rows are selected.